In general, there has been a tendency to increase the diameter of a wafer in current semiconductor fabrication processes so as to accomplish high integration of a ULSI (ultralarge scale integrated circuit). Also, current semiconductor fabrication has been subjected to more strict standards including the minimum width requirement of 0.13 μm or less. Further, a step of forming a multiple interconnection or multilayer interconnection structure on a wafer is essentially required for improving the quality of a semiconductor device. However, non-planarization of wafer occurring after carrying out one of the above techniques causes many problems, such as a drop in the margin in the subsequent steps or degradation of the quality of a transistor or device. Therefore, planarization processes have been applied to various steps so as to solve such problems.
One of these planarization techniques is CMP (chemical mechanical polishing). During the process of CMP, a wafer surface is pressed against a polishing pad that rotates relative to the surface, and chemically reactive slurry is introduced into the polishing pad during the polishing process. Such a CMP technique accomplishes planarization of a wafer surface by way of chemical and physical actions.
Such a CMP technique may be applied to a shallow trench isolation (STI) process, and particularly in a step of polishing an insulating silicon oxide layer 104 until a silicon nitride etch-stop layer 102 is exposed, after depositing the insulating silicon oxide layer 104 so that a trench 103 on a wafer may be embedded therein (see (b) and (c) in FIG. 1). Herein, the silicon nitride layer has a higher strength and hardness as compared to the silicon oxide layer by about three times, and thus the polishing rate of the silicon oxide layer is higher than that of the silicon nitride layer. It is preferable that no silicon nitride layer is removed. In other words, it is ideal that the polishing rate of the silicon oxide layer to the silicon nitride layer (referred to also as ‘polishing selectivity of the insulating silicon oxide layer to the silicon nitride layer’ hereinafter) is infinite.
However, conventional CMP slurry has a low polishing selectivity of the insulating silicon oxide layer to the silicon nitride layer, which is about 4:1. Hence, the silicon nitride layer is polished to a degree exceeding the acceptable range in a practical CMP process. As a result, the silicon nitride layer pattern may be removed non-uniformly depending on locations in a wafer during a CMP process. Therefore, the silicon nitride etch-stop layer has a significantly variable thickness over the whole wafer. During an STI process, this causes a level difference between active regions and field regions in a final structure having a trench formed thereon, resulting in a drop in the process margin of the subsequent steps for manufacturing a semiconductor device, and degradation of the quality of a transistor and a device. Particularly, this is a serious problem in the case of a semiconductor wafer that has patterns having different densities at the same time.
In addition to the aforementioned problem of local planarization, the conventional CMP process shows low within-wafer non-uniformity (WIWNU). In other words, during the polishing according to the conventional CMP process, the central portion of a wafer is predominantly polished as compared to the circumferential portion thereof, resulting in formation of a longitudinal section having a U-like or W-like overall shape. It is thought that this is because the mechanical pressure pressurizing the wafer and polishing pad is distributed non-uniformly, so that the polishing slurry or polishing particles cannot be distributed uniformly and the central portion of the wafer is subjected to a relatively high polishing rate.
To solve the above problem related with WIWNU, a practical semiconductor fabrication process adopts a larger processing margin for a silicon nitride layer so as to ensure reliable termination of CMP. For example, the silicon nitride layer has a larger initial thickness to compensate for the difference in thickness of the silicon nitride layer between the central portion and the circumferential portion of the wafer after polishing. However, this results in degradation of the cost-efficiency of the process.